The present invention relates to a system and method for synchronizing multiple processing modes in a computer, and more particularly relates to a system and method for efficiently providing mutually exclusive access to a computer resource that is shared by distinct processing modes executed by a microprocessor.
In the operating systems and hardware that are employed in most personal computers, interrupts have traditionally been handled by the operating system. This allows the interrupt handling routines to be synchronized or coordinated with other processes that are under the control of the operating system, thereby resulting in reliable and efficient operation of the computer system. The ability to synchronize multiple processes is important regardless of whether the processes are executed on a single processor or on a multi-processor system.
Asynchronous processes are frequently synchronized by using xe2x80x9csemaphores,xe2x80x9d which are signals or flags that govern access to shared system resources. Mutually exclusive access to a shared resource is necessary when a resource does not lend itself to shared access by multiple processes or when sharing would result in an unpredictable outcome. A xe2x80x9cmutexxe2x80x9d is a type of semaphore that is used to ensure that access to the shared resource is mutually exclusive, i.e., that, at any given time, only one process has access to the shared resource. A process must acquire the mutex before it can access a shared resource. Once the process is finished with the shared resource, the process xe2x80x9creturnsxe2x80x9d the mutex so that it is available to be acquired by other processes that need to access the shared resource. A mutex may be used in the context of a locking mechanism known as a xe2x80x9cspin lock.xe2x80x9d If the process is unable to acquire the mutex, the process simply continues to try until it is successful.
Although synchronization is very important for reliable and efficient operation, some microprocessors provide processing modes that are hidden from the operating system. For example, the xe2x80x9cx86xe2x80x9d architecture, which includes Intel Corporation""s xe2x80x9cPENTIUMxe2x80x9d and xe2x80x9c80486xe2x80x9d microprocessors, implements a system management mode (SMM). SMM is an extremely privileged processor mode, which provides a mechanism for incorporating software controlled features that operate transparent to program modules such as the operating system and application programs. SMM is intended for use only by the computer system""s firmware, not by application programs and operating system software.
In the x86 architecture, the microprocessor enters system management mode when it receives a system management interrupt (SMI). The SMM code is typically hidden from the operating system by storing it in a dedicated and secure memory space referred to as SMM RAM. The SMM RAM is used to store the SMI handler code and CPU context data. The microprocessor provides a status signal that the computer system hardware uses to decode access to the SMM RAM. An RSM instruction causes the microprocessor to exit SMM.
The SMM is transparent to the operating system and application programs for the following reasons: (1) the only way to enter SMM is by providing a non-maskable type of interrupt triggered by an external signal applied to the appropriate pin on the microprocessor; (2) the processor begins executing SMM code from a separate address space (SMM RAM); (3) upon entering SMM, the processor saves the register state of the interrupted program module in a portion of the SMM RAM; (4) upon entering SMM, all interrupts normally handled by the operating system or by applications are disabled; and (5) the RSM instruction restores processor registers from the SMM RAM and returns control to the interrupted program module.
Although processing modes such as SMM provide a mechanism for implementing power management and other features in a computer, the SMM is incompatible with the operating system and takes control of the computer away from the operating system. An SMI can stop the processor at any time, including in the middle of some instructions. The lack of synchronization and cooperation between the SMM processing mode and the operating system processing mode results in decreased reliability and efficiency. The lack of synchronization also makes it difficult for the operating system and SMM to reliably share access to the computer""s resources.
In some cases, it is desirable for the SMM and operating system to share access to some hardware resources. However, prior art synchronization mechanisms are inadequate or inefficient when attempting to provide synchronization between the SMM processing mode and the operating system processing mode. For example, if the SMM processing mode fails to acquire a spin lock because the mutex is in use by the operating system, the system will fail because the SMM interrupts the operating system and prevents the operating system from completing its operation and freeing the mutex. In other locking mechanisms, a process may xe2x80x9cannouncexe2x80x9d that it has released a lock. If this approach were used with the SMM environment, it would require that the operating system generate an SMI every time it released the mutex, in order to notify the SMM that the lock is available. Because of the overhead and problems associated with switching between the operating system environment and the SMM environment, such an approach would be highly inefficient at best.
Therefore, there is a need in the art for an efficient locking mechanism that can be used to synchronize two distinct processing modes, such as the operating system and SMM processing modes. Each processing mode should be required to acquire the lock prior to using particular resources, and to release the lock in a manner that allows efficient acquisition by the other environment.
The present invention satisfies the above-described needs by providing an intermodal locking mechanism that allows synchronization between two processing modes and that ensures mutually exclusive access to system resources that are shared by the two processing modes. In order to synchronize first and second processing modes and allow mutually exclusive access to shared resources, the computer system includes shared memory, which contains the intermodal lock, and a mechanism for allowing each processing mode to signal the other processing mode. Before either processing mode can access the shared resource, the processing mode must attempt to acquire the intermodal lock. If the intermodal lock is acquired, the processing mode may access the shared resource. If the intermodal lock is not acquired, the processing mode sets a pending bit and resumes other tasks until it receives a lock release signal from the other processing mode. When a processing mode has finished accessing the shared resource, it releases the intermodal lock and checks to see if the pending bit is set. If so, the processing mode sends a lock release signal to the other mode. This allows disparate processing modes to efficiently share a resource and ensures mutually exclusive access to the resource.
Generally described, the present invention provides a method for synchronizing first and second processing modes executed by a processing unit and for controlling access to a shared resource. The method includes providing a lock that is accessible to the first and second processing modes and which indicates the availability of access to a shared resource. The first processing mode attempts to acquire the lock. If the lock is acquired by the first processing mode, the first processing mode accesses the shared resource. The first processing mode releases the lock after accessing the shared resource from the first processing mode, and then determines the status of a pending indicator associated with the lock. If the pending indicator was set, the first processing mode sends a signal to the second processing mode.
More particularly described, the present invention attempts to acquire the lock by reading a value in a data register associated with the lock and retaining copies of the value as an original lock value and an altered lock value. An owned bit is set in the altered lock value. The first processing mode determines whether an owned bit in the original lock value is set. If so, the first processing mode sets a pending bit in the altered lock value. The first processing mode then determines whether the value in the data register associated with the lock remains equal to the value stored in the original lock value. If so, the first processing mode stores the altered lock value in the data register associated with the lock.
Still more particularly described, the present invention releases the lock by reading a value in a data register associated with the lock and retaining the read value as an original lock value and an altered lock value. The first processing mode clears an owned bit and a pending bit in the altered lock value. The first processing mode determines whether the value in the data register associated with the lock remains equal to the original lock value. If so, the first processing mode stores the altered lock value in the data register associated with the lock.
In another aspect, the present invention provides a computer system that includes a processing unit capable of executing first and second processing modes, a shared resource accessible to the first and second processing modes, and a lock for controlling access to the shared resource. The lock includes a lock data register accessible to the first and second processing modes. In response to instructions from a program module, the processing unit is operative to attempt to acquire the lock from a first processing mode. If the lock is acquired, the first processing mode accesses the shared resource. Otherwise, the first processing mode sets a pending indicator. The first processing mode releases the lock after accessing the shared resource and determines whether a pending indicator is set. If so, the processing unit sends a signal to the second processing mode.
In another aspect, the present invention provides a computer-readable medium on which is stored a computer program for synchronizing first and second processing modes executed by a processing unit and for controlling access to a shared resource. The computer program comprising instructions which, when executed by the processing unit, perform the steps of providing a lock for controlling access to the shared resource. The lock includes a register accessible to the first and second processing modes and indicates the availability of access to the shared resource. The program steps cause the first processing mode to attempt to acquire the lock. If the lock is acquired, the first processing mode accesses the shared resource. The program releases the lock after accessing the shared resource and determines the status of a pending indicator. If the pending indicator is set, the programs sends a signal to the other processing mode.
The various aspects of the present invention provide a mechanism for synchronizing processing modes to coordinate activities that run the computer. In addition, the present invention provides a mutually exclusive lock that is accessible by separate processing modes. The present invention also provides intermode communication to alert pending mode that the lock is no longer owned. The various aspects of the present invention may be more clearly understood and appreciated from a review of the following detailed description of the disclosed embodiments and by reference to the appended drawings and claims.